Astera Labs and AMD have been jointly innovating to take CXL® from concept to reality. Together, we are delivering real silicon that runs real workloads. In this video, we take you to the lab to watch a live demonstration of Leo Smart Memory Controllers and 4th Gen AMD EPYC™ Processors.

Learn more about CXL™ Technology

CXL Demo for DLRM at OCP Summit 2024

See how Leo and 5th Gen AMD EPYC processors deliver a 70% performance boost for DLRM with CXL.

OCP Global Summit Booth Tour

Take a 360 degree tour of Astera Labs' booth at OCP Global Summit 2024.

AI Inferencing Demo with CXL®-Attached Memory: FMS 2024

This award-winning demo shows how AI inferencing can gain significant benefits using CXL®-attached memory.

Unprecedented Scale for AI Infrastructure: OCP 2023

Astera Labs’ PCIe®, CXL®, and Ethernet connectivity solutions deliver unprecedented reach, unprecedented memory capacity and bandwidth, and unprecedented...

Leo CXL® Memory Controllers Break Through the Memory Wall

See how Leo CXL® Smart Memory Controllers combined with 5th Gen Intel Xeon Scalable Processors increase memory bandwidth and capacity by 50%.

Interop Testing with Leo and DDR5-5600 RDIMMs

Learn about industry-first interoperability testing between Leo and DDR5-5600 RDIMMs from Micron, Samsung, and SK hynix.

Astera Labs Advances CXL® Technology Ecosystem

Related Links