Leo Interop

Ensuring plug-and-play interoperability for the growing CXL® ecosystem

Deploy CXL-attached memory at scale with confidence

  • Rigorous testing of Leo Memory Controllers with industry-leading hosts, memory, and operating systems
  • Comprehensive testing including PCIe electrical, memory, CXL® compliance and system level for end-to-end coverage
  • Extensive testing with COSMOS software suite for Link, Fleet and RAS telemetry and diagnostics

Interop Bulletins

Hardware and Software Coverage

Example Tests

CXL® Compliance Tests

  • PCIe Electrical Testing
  • Transaction Layer Testing
  • Arbitrator and Multiplexer
  • Power Management Tests
  • Reset and Initialization Tests

System & Memory Tests

  • DDR Tests
  • Stress Tests
  • Traffic Tests
  • Security Tests
  • Reliability, Availability, and Serviceability

Seven Key Innovations Shaping AI Connectivity Showcased at DesignCon 2025

Astera Labs will be at DesignCon 2025, taking place January 28-30 at the Santa Clara Convention Center, to showcase our latest chip, board, and system design innovations for AI and cloud infrastructure.Join us at Booth #755 to see our Intelligent Connectivity Platform of PCIe®, Ethernet, and CXL® connectivity solutions in action and learn how we are unleashing the full potential of…

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Accelerating the PCIe 6.x Ecosystem: Industry-First PCIe 6.x Interop Demonstration at DesignCon

Astera Labs has teamed up with Micron to deliver another industry-first technology development and accelerate the PCIe® 6.x ecosystem! At DesignCon 2025 in Astera Labs Booth #755, the two companies are showcasing the first public demonstration of end-to-end interoperability between a PCIe 6.x Switch and a PCIe 6.x SSD, currently available for ecosystem development.The demo features Astera…

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The Need for Modular AI Server Solutions

The incredible pace of hardware and software innovations across CPUs, accelerators (such as GPUs), and AI training and inference models is yielding ever-expanding benefits across virtually all sectors of society. However, the disjointed pace of these separate evolutionary paths introduces three main challenges:Mixed-generation components can cause bandwidth mismatches and inefficiencies.Reliability…

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Astera Labs Announces Conference Call to Review Fourth Quarter 2024 Financial Results

SANTA CLARA, CA, U.S. – Jan. 9, 2025 – Astera Labs, Inc. (Nasdaq: ALAB), a global leader in semiconductor-based connectivity solutions for AI and cloud infrastructure, today announced that it will release its financial results for the fourth quarter 2024 after the close of market on Monday, Feb. 10, 2025. Astera Labs will host a corresponding conference call at 1:30 p.m. Pacific…

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Astera Labs Announces Financial Results for the Third Quarter of Fiscal Year 2024

Record quarterly revenue of $113.1 million, up 47% QoQ and up 206% YoY Expanding market opportunities with new Scorpio Fabric Switches, driving higher dollar content in AI platformsSANTA CLARA, CA, U.S. – November 4, 2024 – Astera Labs, Inc. (Nasdaq: ALAB), a global leader in semiconductor-based connectivity solutions for cloud and AI infrastructure, today announced preliminary…

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Astera Labs Introduces New Portfolio of Fabric Switches Purpose-Built for AI Infrastructure at Cloud-Scale

Shipping in pre-production quantities, Scorpio Smart Fabric Switches deliver maximum system utilization and uptime for scale-out PCIe 6 connectivity and scale-up GPU clustering in AI serversSANTA CLARA, CA, U.S. – October 8, 2024 – Astera Labs, Inc. (Nasdaq: ALAB), a global leader in semiconductor-based connectivity solutions for AI and cloud infrastructure, today announced a new…

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Astera Labs Announces Conference Call to Review Third Quarter 2024 Financial Results

SANTA CLARA, CA, U.S. – Oct. 2, 2024 – Astera Labs, Inc. (Nasdaq: ALAB), a global leader in semiconductor-based connectivity solutions for AI and cloud infrastructure, today announced that it will release its financial results for the third quarter 2024 after the close of market on Monday, Nov. 4, 2024. Astera Labs will host a corresponding conference call at 1:30 p.m. Pacific…

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Interop Testing with Linux Operating Systems and Leo

Learn how Astera Labs is enabling the CXL ecosystem with software support to support disaggregated memory architectures. Astera Labs is working closely with operating system vendors to ensure robust compatibility with Linux environments.In its Cloud-Scale Interop Lab, Astera Labs has successfully completed interoperability with enterprise-grade Linux operating systems from Red Hat and S…

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PCIe Cabling Demo at OCP 2024

At OCP Global Summit 2024, Astera Labs demonstrated its full portfolio of PCIe cabling solutions. The live demos included Aries PCIe/CXL Smart Cable Modules with Active Electrical Cables and Active Optical Cables to deliver extended reach for rack-to-rack and row-to-row configurations.

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CXL Demo for DLRM at OCP Summit 2024

At OCP Global Summit, Astera Labs demonstrated the performance benefits of CXL memory for Deep Learning Recommendation Models (DLRM). The demo featured a 5th Gen AMD EPYC processor, DDR5 memory from Samsung, and four Leo CXL Smart Memory Controllers. The demo showed that by doubling memory capacity and bandwidth in the system, there is about a 70% increase in performance for DLRM.

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