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HPC: Computer Aided Engineering

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CXL Interleaving Up to 50%+ Performance Improvement for HPC Workloads

Constrained Memory Footprint for HPC Cluster
Without CXL

Challenge:​

  • HPC workloads push CPUs to their thermal design limits
  • Compute blades have limited space for large memory footprint
  • Insufficient memory bandwidth can slow down HPC performance
  • Untuned memory tiering solutions may lead to unpredictable performance

Expanded Memory Footprint for HPC Cluster
With CXL

Solution:

  • 12-way interleaving boosts HPC performance by 1.5x
  • 5th Gen Intel Xeon CPUs offer plug-and-play memory tiering support
  • Leo CXL Smart Memory Controllers enable thermally optimized designs
  • Flexible memory expansion options for high-density compute blade

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