Learn how Leo CXL® Smart Memory Controllers not only unlock the many exciting benefits of CXL technology, but also deliver server-grade customizable Reliability, Availability and Serviceability, end-to-end security, extensive fleet management capabilities and seamless interoperability with all major CPU, GPU and memory vendors for cloud-scale deployment.

Learn more about Leo CXL Memory Connectivity Platform

Interop Testing with Linux Operating Systems and Leo

Learn how Astera Labs is enabling the CXL ecosystem with software support to support disaggregated memory architectures.

CXL Demo for DLRM at OCP Summit 2024

See how Leo and 5th Gen AMD EPYC processors deliver a 70% performance boost for DLRM with CXL.

OCP Global Summit Booth Tour

Take a 360 degree tour of Astera Labs' booth at OCP Global Summit 2024.

AI Inferencing Demo with CXL®-Attached Memory: FMS 2024

This award-winning demo shows how AI inferencing can gain significant benefits using CXL®-attached memory.

Unprecedented Scale for AI Infrastructure: OCP 2023

Astera Labs’ PCIe®, CXL®, and Ethernet connectivity solutions deliver unprecedented reach, unprecedented memory capacity and bandwidth, and unprecedented...

Leo CXL® Memory Controllers Break Through the Memory Wall

See how Leo CXL® Smart Memory Controllers combined with 5th Gen Intel Xeon Scalable Processors increase memory bandwidth and capacity by 50%.

Unlock the Full Potential of CXL® with Leo Smart Memory Controllers