Higher bandwidth PCIe® 6.x technology is required to maximize utilization of GPUs, CPUs, and AI accelerators to meet the performance demands of new AI workloads in hyperscale systems; however, this creates new connectivity issues with increases in speed, complexity, and scale. These challenges emphasize the need for extensive testing to ensure robust interoperability between the wide variety of PCIe 6.x components within an AI system deployed at cloud-scale.
Read more Leo Interop with Intel Xeon 6 Processors
Astera Labs has completed successful interop testing between Leo CXL Smart Memory Controllers and Intel Xeon 6 Processors.
